The present invention relates to first-in-first-out memories (FIFOs) for integrated circuits, and more particularly to distributed FIFOs for field programmable gate arrays (FPGAs).
The size, complexity, and functionality of field programmable gate array integrated circuits have been increasing at a tremendous rate the last several years. FPGA devices now include thousands of configurable or programmable cells such as configurable logic gates and I/O cells, programmable interconnect, memories, and other types of circuits. These circuits are often intermixed on an integrated circuit, such that various logic blocks have routing access to memories, I/O cells, and other included circuitry.
The optimal size and distribution of memories on an FPGA or other configurable device has been the subject of much study and analysis. Typically, it is desirable to have several small local memory arrays distributed about on an FPGA integrated circuit. When a circuit formed from configurable logic needs to use memory resources, this arrangement allows easy access. In particular, having a small local memory nearby reduces the length of interconnect lines to the memory, which saves valuable routing resources and reduces stray capacitance, thereby saving power and reducing gate delay times.
But on occasion it is desirable to have a larger memory. For example, a circuit function may require a FIFO that is larger than a particular local memory array. In this case, two or more local memory arrays can be combined into a single functional unit.
When this occurs, the length of the interconnect lines used to reach the more distant memory arrays become long. The problems that were sought to be remedied by the use of smaller local memories return. That is, longer interconnect lines, which consume routing resources that could be better spent and result in larger stray capacitances that slow circuit signal paths, are needed.
Thus, it is desirable to have improved FIFO architectures that are formed from several smaller memory arrays in such a way as to reduce the number and length of interconnect lines. It is further desirable to reduce the number and length of necessary interconnect lines without dramatically increasing the complexity of circuitry included in the FIFO.